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Micron Webinar: Has “more confidence in the next several years of scaling on both DRAM and NAND than we have in quite some time,” supporting continued cost and performance improvements.
- No memory supply-demand balance in sight: Management reiterated shortages over the next two years and added, “we actually don’t see a time when it comes into balance.” Different AI rack architectures may change the mix of LPDRAM, DDR and HBM, but management expects all to remain memory-intensive.
- 1-delta DRAM volume ramp targeted for 2H27, including manufacturing in Boise, with a mid-20s percentage bit-density improvement versus 1-gamma. The node is optimized for HBM5, vertical HBM and vertical edge-inference memory; 1-gamma underpins key products launching over the next 12 months.
- G11 NAND ramps in 2H27, targeting 2x G9 bit density, 1.5x I/O speed and lower data-transfer energy, using wafer-on-wafer bonding and more than 400 layers. Micron deliberately made a larger generational leap to optimize for future AI requirements; higher-performance AI-class NAND products are targeted over the next couple of years.
- Wafer-consumption pressure increases across the roadmap: HBM, vertical HBM and vertical edge-inference memory require progressively more wafers relative to standard DRAM bits. Vertical HBM’s larger I/O count further reduces dies per wafer; thermal constraints initially limit stack capacity, so many systems are expected to combine vertical HBM for bandwidth with conventional HBM5E for capacity.
- HBM4 is in high-volume manufacturing with a “very successful” ramp. HBM4E requires more advanced CMOS for speed and power optimization; both standard and custom products will use advanced foundry base dies. Vertical HBM continues that approach, with increasing functionality moved from the accelerator into the memory base die.
- LPDDR6 targets roughly 35% lower power versus LPDDR5, with larger benefits at some densities; DDR6 targets 2x DDR5 bandwidth. Micron is collaborating with Meta to optimize LPDDR6 for data centers and plans a 1TB RDIMM following its recently sampled 512GB module.
- On potential memory “despeccing,” management acknowledged customers will optimize minimum requirements and that smaller models and edge workloads need different configurations. Its underlying view remains that more memory capacity and bandwidth improve system performance; the response did not quantify any near-term content reductions.
- AI tools are already shortening execution cycles: cited examples include 50% less development time for a data-center SSD controller and 60% less time for an entire data-center SSD product. Management is explicitly depending on faster execution and greater engineering capacity to address the expanding range of customer-specific requirements.
- Confidence in several more planar DRAM nodes and continued NAND scaling is higher than it has been “in quite some time.” 3D DRAM remains a parallel development path, with deployment determined by cost, complexity and performance rather than a fixed transition date. The previously announced $10B research-lab investment over 10 years extends work beyond current product roadmaps.
- 1-delta DRAM volume ramp targeted for 2H27, including manufacturing in Boise, with a mid-20s percentage bit-density improvement versus 1-gamma. The node is optimized for HBM5, vertical HBM and vertical edge-inference memory; 1-gamma underpins key products launching over the next 12 months.
- G11 NAND ramps in 2H27, targeting 2x G9 bit density, 1.5x I/O speed and lower data-transfer energy, using wafer-on-wafer bonding and more than 400 layers. Micron deliberately made a larger generational leap to optimize for future AI requirements; higher-performance AI-class NAND products are targeted over the next couple of years.
- Wafer-consumption pressure increases across the roadmap: HBM, vertical HBM and vertical edge-inference memory require progressively more wafers relative to standard DRAM bits. Vertical HBM’s larger I/O count further reduces dies per wafer; thermal constraints initially limit stack capacity, so many systems are expected to combine vertical HBM for bandwidth with conventional HBM5E for capacity.
- HBM4 is in high-volume manufacturing with a “very successful” ramp. HBM4E requires more advanced CMOS for speed and power optimization; both standard and custom products will use advanced foundry base dies. Vertical HBM continues that approach, with increasing functionality moved from the accelerator into the memory base die.
- LPDDR6 targets roughly 35% lower power versus LPDDR5, with larger benefits at some densities; DDR6 targets 2x DDR5 bandwidth. Micron is collaborating with Meta to optimize LPDDR6 for data centers and plans a 1TB RDIMM following its recently sampled 512GB module.
- On potential memory “despeccing,” management acknowledged customers will optimize minimum requirements and that smaller models and edge workloads need different configurations. Its underlying view remains that more memory capacity and bandwidth improve system performance; the response did not quantify any near-term content reductions.
- AI tools are already shortening execution cycles: cited examples include 50% less development time for a data-center SSD controller and 60% less time for an entire data-center SSD product. Management is explicitly depending on faster execution and greater engineering capacity to address the expanding range of customer-specific requirements.
- Confidence in several more planar DRAM nodes and continued NAND scaling is higher than it has been “in quite some time.” 3D DRAM remains a parallel development path, with deployment determined by cost, complexity and performance rather than a fixed transition date. The previously announced $10B research-lab investment over 10 years extends work beyond current product roadmaps.